1. Field of the Invention
This invention pertains generally to resistance-sensing based random access memory (RAM) devices, and more particularly to a short pulse reading (SPR) circuit implementation based on a body-voltage sensing circuit (BVSC).
2. Description of Related Art
Research efforts in the memory industry have continued towards providing a scalable “universal memory”. Among many candidates, are (1) phase-change RAM (PC-RAM) which has been shown to be a good replacement for Flash memory; (2) resistive RAM (ReRAM) which is in its initial stage of exploration; (3) magnetoresistive RAM (MRAM); and (4) spin-torque transfer RAM (STT-RAM) which has been regarded as the front runner.
It has been demonstrated that STT-RAM can achieve smaller cell size than static RAM (SRAM), greater performance than dynamic RAM (DRAM), the non-volatility of Flash and improved endurance that is on the order of 1016 read/write cycles. Compared to MRAM, another advantage of STT-RAM is that the switching current of its storage device, a magnetic tunnel junction (MTJ), scales with device size due to the nature of spin-torque transfer. As a result, both the CMOS and MTJ devices appear promising for being further scaled down in advanced STT-RAM technology node toward realizing higher memory density and lower power consumption. Although, scaling reduces the critical current density (JC) of the MTJ and increases the variability of both devices, impeding the reading operations from being reliable and high speed.
Existing reading circuit designs typically adopt the low current reading (LCR) scheme, in which a sensing current smaller than the writing current is applied on the selected MTJ to avoid read disturbance. FIG. 1 shows a current-mirror sensing circuit (GMSC). This design adds an equalizer to the current mirror sense amplifier outputs to mitigate the issues of the imbalanced output impedance and the skewed sensing time of reading RP and RAP. FIG. 2 shows a split-path sensing circuit (SPSC). This design implements a double current-mirror based differential amplifier by splitting the sensing current into two paths and mirroring them differentially to improve its output signal swing and read margin (RM). Both of the above designs utilize the LCR scheme.
In the LCR based sensing circuit designs, the sensing current is strictly bounded by the long duration switching current (IC) of the MTJ. Consequently, JC scaling would eventually create difficulty in achieving high reading speed for this sensing scheme. To solve this problem, a short pulse reading (SPR) method has been considered which uses a sensing current similar to the writing current in magnitude, but with a much shorter pulse width, to read the MTJ.
However, no circuit implementations of a short pulse reading (SPR) scheme has been advanced, and no answers have arisen as to the best circuit structure to implement an SPR based high-performance STT-RAM.